#MCell 4.00
#GAME Rules table
#RULE 1,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,0,3,3,3,3,3,3,3,3,3,
#RULE 0,3,1,1,3,3,3,3,3,3
#BOARD 80x60
#SPEED 100
#WRAP 0
#CCOLORS 4
#PALETTE 8 colors
#D In the above file we have a couple of NOT gates (top middle),
#D an XOR gate (bottom left) and a NAND gate (right).
#D 
#D The inelegant part of these NOT and NAND gates is that they
#D have internal clocks -- a pulse arriving must be in sync with the
#D internal clock or the gate will fail to function.
#D 
#D I don't believe this can be helped, but an OR gate only requires that the
#D incoming pulses be in sync, which is seems to be a much nicer property.
#D On the other hand, the NAND gate does have a certain visual appeal.
#D 
#D George Phillips, February 1990
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