#MCell 4.00
#GAME Rules table
#RULE 1,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,0,3,3,3,3,3,3,3,3,3,
#RULE 0,3,1,1,3,3,3,3,3,3
#BOARD 80x40
#SPEED 100
#WRAP 0
#CCOLORS 4
#PALETTE 8 colors
#D On the left is an AND gate and on the right is a NAND gate being
#D fed test patterns. The AND gate on the left is unfortunate: internally
#D clocked and is really only A & B * ~(~A | ~B). Happily, I found
#D a non-clocked AND gate (bottom right). The key is the "H" pattern
#D near the output -- it does that actually ANDing. But 2 '1' pulses break
#D the gate, so the one signal must be multiplied into 2 electrons (by the G)
#D with the second electron stopping any out of control oscillations.
#D 
#D George Phillips, February 1990
#L 12.C.CC43.CC$11.3C..C41.C..C$9.CC.C.C.C18.4CBA5C10.CC..3C$8.C5.C.C17.C
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#L 5.C.C4.C..A9.A11.C8.C5.C..CC$9.CC.C.C.C5.CC11.11C10.CC..3C$11.3C..C41.
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#L BAC3.4C$27.A6C27.3C